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FAN8036
5-CH Motor Driver + 2-Regulator
Features
* * * * * * * * * 4-CH Balanced Transformerless (BTL) Driver 1-CH (Forward Reverse) Control DC Motor Driver Operating Supply Voltage (4.5V ~ 13.2V) Built in Thermal Shut Down Circuit (TSD) Built in Channel Mute Circuit Built in Power Save Mode Circuit Built in TSD Monitor Circuit Built in 2 Regulators Built in 2-OP AMPs
Description
The FAN8036 is a monolithic integrated circuit suitable for a 5-CH motor driver which drives the tracking actuator, focus actuator, sled motor, spindle motor, and tray motor of the CDP/CAR-CD/DVDP systems.
48-QFPH-1414
Typical Application
* * * * Compact Disk Player Video Compact Disk Player Car Compact Disk Player Digital Video Disk Player
Ordering Information
Device FAN8036L Package 48-QFPH-1414 Operating Temperature -35C ~ +85C -35C ~ +85C
FAN8036_NL 48-QFPH-1414
Rev. 1.0.1
(c)2003 Fairchild Semiconductor Corporation
FAN8036
Pin Assignments
IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF 48 47 46 45 44 43
FIN (GND)
REGVCC OPIN2+ OPIN2- OPOUT2 PVCC1 DO1+ 42 41 40 39 38 37
IN1-
1
36
DO1-
OUT1 IN2+
2
35
DO2+
3
34
DO2-
IN2-
4
33
PGND1
OUT2 RES1
5
32
REGO1
6
31
REGO2
FIN (GND)
FAN8036
7 30
FIN (GND)
RES2
DO3+
REGCTL
8
29
DO3-
IN3+ IN3-
9
28
DO4+
10
27
DO4-
OUT3
11
26
PGND2 DO5+
IN4+
12
25
13 IN4-
14 OUT4
15 CTL
16 FWD
17
18
19
20
21 PS
22
23
24 DO5-
REV SGND
FIN MUTE123 MUTE4 (GND)
TSD_M PVCC2
2
FAN8036
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IN1- OUT1 IN2+ IN2- OUT2 RES1 RES2 REGCTL IN3+ IN3- OUT3 IN4+ IN4- OUT4 CTL FWD REV SGND MUTE123 MUTE4 PS TSD-M PVCC2 DO5- DO5+ PGND2 DO4- DO4+ DO3- DO3+ REGO2 REGO1 I/O I O I I O I I I I I O I I O I I I I I I O O O O O O O O O Pin Function Descrition CH1 OP-AMP Input (-) CH1 OP-AMP Output CH2 OP-AMP Input (+) CH2 OP-AMP Input (-) CH2 OP-AMP Output Regulator1 Reset Regulator2 Reset Regulator2 Control Voltage CH3 OP-AMP Input (+) CH3 OP-AMP Input (-) CH3 OP-AMP Output CH4 OP-AMP Input (+) CH4 OP-AMP Input (-) CH4 OP-AMP Output CH5 Motor Speed Control CH5 Forward Input CH5 Reverse Input Signal Ground Mute for CH1,2,3 Mute for CH4 Power Save TSD Monitor Power Supply Voltage 2 (for CH3,CH4,CH5) CH5 Drive Ouptut (-) CH5 Drive Output (+) Power Ground 2 (for CH3,CH4,CH5) CH4 Drive Ouptut (-) CH4 Drive Output (+) CH3 Drive Ouptut (-) CH3 Drive Output (+) Regulator2 Ouptut Regulator1 Ouptut
3
FAN8036
Pin Definitions (Continued)
Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name PGND1 DO2- DO2+ DO1- DO1+ PVCC1 REGVCC OPOUT2 OPIN2- OPIN2+ VREF SVCC OPOUT1 OPIN1- OPIN1+ IN1+ I/O O O O O O I I I O I I I Pin Function Descrition Power Ground 1 (for CH1, CH2) CH2 Drive Ouptut (-) CH2 Drive Output (+) CH1 Drive Ouptut (-) CH1 Drive Output (+) Power Supply Voltage 1 (for CH1, CH2) Regulator Supply Voltage( Regulator1,2) Normal OP-AMP2 Output Normal OP-AMP2 Input (-) Normal OP-AMP2 Input (+) Bias Voltage Input Signal & OPAMPs Supply Voltage Normal OP-AMP1 Output Normal OP-AMP1 Input (-) Normal OP-AMP1 Input (+) CH1 OP-AMP Intput (+)
4
FAN8036
Internal Block Diagram
FIN (GND) REGVCC OPIN2+ OPIN2- OPOUT2 PVCC1 DO1+ 42 41 40 39
REGVCC
IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF 48 47 46 45 44 43
38
37
IN1-
1
36
DO1-
OUT1 IN2+
2
35
DO2+
3
34
DO2-
IN2-
4 REGVCC REGVCC
33
PGND1
OUT2 RES1
5
32
REGO1
6 TSD
31
REGO2
FIN (GND)
REGVCC REGVCC
FIN (GND)
RES2
7
30
DO3+ DO3DO4+
REGCTL IN3+
8
29
9
28
IN3OUT3
10 M S C + PS D D
27
DO4-
11
S W
26
PGND2 DO5+
IN4+
12
25
MUTE123 MUTE4 TSD_M
13 IN4-
14 OUT4
15 CTL
16 FWD
17
18
19
20
21 PS
22
23
24 DO5-
REV SGND
FIN MUTE123 MUTE4 (GND)
TSD_M PVCC2
5
FAN8036
Equivalent Circuits
Description Pin No Internal Circuit
VCC
VCC
2K 2K
1 10 46 4 13
BTL INPUT & OP AMP1 INPUT
48,3,9,12,47 1,4,10,13,46
48 9
3 12 47
VCC
5K 5K
VCC
OP AMP2 INPUT
41,42
42 41
VCC
1K 5K
VCC
VREF
43
43
1K
VCC
VCC
BTL OP AMP OUT OP AMP1 OUT
2,5,11,14,45
2 11
5 14 45
6
FAN8036
Equivalent Circuits (Continued)
Description Pin No Internal Circuit
VCC
VCC
OP AMP2 OUT
40
40
0.05K 0.05K
VCC
20K
MUTE123,4
19,20
19 20
50K 50K
VCC
CTL
15
15
1K
39K
TSD-M
22
22
20k
7
FAN8036
Equivalent Circuits (Continued)
Description Pin No Internal Circuit
VCC
100k
PS
21
21
50K 50K
VCC
30K
FWD,REV
16,17
16 17
30K 30K
30K
freewheeling diode VCC vcc
BTL CH1,2,3,4 OUTPUT
27 29 34 36 28 30 35 37
VCC
27,28,29,30, 34,35,36,37
40K 7K
parastic diode
freewheeling diode VCC vcc
VCC
BTL CH5 OUTPUT
24,25
24
25
60K 7K
parastic diode
8
FAN8036
Equivalent Circuits (Continued)
Description Pin No Internal Circuit
REGVCC
39
10K
REGO1,2
31,32
31
10K 10K
32
VCC
RES1,2
6,7
6 7
50K 50K
VCC
VCC
REGCTL
8
8
2K 10K
9
FAN8036
Absolute Maximum Ratings ( Ta=25C)
Parameter Symbol SVCCMAX Maximum Supply Voltage PVCC1 PVCC2 REGVCC Power Dissipation Operating Temperature Storge Temperature Maximum Output Current PD TOPR TSTG IOMAX Value 18 18 18 18 3
note
Unit V V V V W C C A
-35 ~ +85 -55 ~ +150 1
Note: 1. When mounted on the PCB of which size is 114mm x 76mm x 1.6mm. 2. Power dissipation is derated with the rate of -24mW/C for TA25C. 3. Do not exceed PD and SOA.
Pd (mW) 3,000 2,000
1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [C]
Recommended Operating Conditions ( Ta=25C)
Parameter Symbol SVCC Operating Supply Voltage PVCC1 PVCC2 REGVCC Min. 4.5 SVCC SVCC 7 Typ. Max. 13.2 13.2 13.2 13.2 Unit V V V V
10
FAN8036
Electrical Characteristics
(SVCC =5V, PVCC1 = PVCC2 = 8V, TA = 25C, unless otherwise specified) Parameter Quiescent Circuit Current Power Save On Current Power Save On Voltage Power Save Off Voltage Mute123 On Voltage Mute123 Off Voltage Mute4 On Voltage Mute4 Off Voltage BTL DRIVER CIRCUIT Output Offset Voltage Maximum Output Voltage1 Maximum Output Voltage2 Closed-loop Voltage Gain Ripple Rejection Ratio Slew Rate*note2 INPUT OPAMP CIRCUIT Input Offset Voltage1 Input Bias Current1 High Level Output Voltage1 Low Level Output Voltage1 Output Sink Current1 Output Source Current1 Common Mode Input Range1 Open Loop Voltage Gain1 Ripple Rejection Ratio1*note2 Common Mode Rejection Ratio1*note2 Slew Rate1
*note2 *note2 *note2 *note2
Symbol ICC IPS
*note1
Conditions Under no-load Under no-load Pin21 = Variation Pin21 = Variation Pin19 = Variation Pin20 = Variation Pin20 = Variation VIN = 2.5V RL = 10, CH1,2 RL = 18, CH3,4,5 VIN = 0.1Vrms VIN = 0.1Vrms, f = 120Hz Square, Vout = 4Vp-p RL = 50 RL = 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p
Min. 2 2 2 -100 4.5 5.5 16.8 1 -10 4.4 1 1 -0.3 -
Typ. 20 6.0 6.5 18 60 2 4.7 0.2 2 2 80 65 80 1.5
Max. 1 0.5 0.5 0.5 +100 19.2 +10 400 0.5 4.0 -
Unit mA mA V V V V V V mV V V dB dB V/s mV nA V V mA mA V dB dB dB V/s
VPSON VPSOFF VMON123 VMON4 VMOFF4 VOO VOM1 VOM2 AVF RR SR VOF1 IB1 VOH1 VOL1 ISINK1 ISOU1 Vicm1 GVO1 RR1 CMRR1 SR1
VMOFF123 Pin19 = Variation
Note : 1. When the voltage at pin 39 goes below 0.5V, the power save circuit makes the main bias current sources stop operating. As a result, the whole circuits are disable. ( The whole circuits mean the driver circuit, the input OP amp circuit, and the normal OP amp circuit.) 2. Guaranteed field.(No EDS/Final test)
11
FAN8036
Electrical Characteristics (Continued)
(SVCC = 5V, PVCC1 = PVCC2 = 8V, TA = 25C, unless otherwise specified) Parameter NORMAL OP AMP CIRCUIT 1 Input Offset Voltage 2 Input Bias Current 2 High Level Output Voltage 2 Low Level Output Voltage 2 Output Sink Current 2 Output Source Current 2 Common Mode Input Range 2 Open Loop Voltage Gain 2 Ripple Rejection Ratio 2*note Common Mode Rejection Ratio 2 Slew Rate 2
*note *note *note *note
Symbol VOF2 IB2 VOH2 VOL2 ISINK2 ISOU2 Vicm2 GVO2 RR2 CMRR2 SR2 VOF3 IB3 VOH3 VOL3 ISINK3 ISOU3 GVO3 RR3
*note
Conditions RL= 50 RL= 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p RL = 50 RL = 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p PVCC2 = 8V, VCTL = 3V, RL= 45 PVCC2 = 8V, VCTL = 1.5V, RL = 10 VCTL=3V, IL=100mA 400mA VIN = 5V, 5V VIN = 0V, 0V
Min. -10 4.4 2 2 -0.3 -15 3 10 10 2 -40 -40
Typ. 4.7 0.2 4 4 80 65 80 1.5 3.8 1.0 80 65 80 1.5 6 3 300 -
Max. +10 400 0.5 4.0 +15 400 1.5 0.5 700 +40 +40
Unit mV nA V V mA mA V dB dB dB V/s mV nA V V mA mA dB dB dB V/s V V V V mV mV mV
NORMAL OP AMP CIRCUIT 2 Input Offset Voltage 3 Input Bias Current 3 High Level Output Voltage 3 Low Level Output Voltage 3 Output Sink Current 3 Output Source Current 3 Open Loop Voltage Gain 3*note Ripple Rejection Ratio 3 Slew Rate 3
*note *note
Common Mode Rejection Ratio 3 TRAY DRIVE CIRTUIT Input High Level Voltage Input Low Level Voltage Output Voltage 1 Output Voltage 2 Output Load Regulation Output Offset Voltage 1 Output Offset Voltage 2
CMRR3 SR3 VIH VIL VO1 VO2 VRL VOO1 VOO2
Note: Guaranteed field.(No EDS/Final test)
12
FAN8036
Electrical Characteristics (Continued)
(SVCC = 5V, PVCC1 = PVCC2 = 8V, TA = 25C, unless otherwise specified) Parameter REGULATOR1 CIRCUIT(REGVCC=8V) Load regulation Line regulation Regulator output voltage 1 Regulator reset on voltage 1 Regulator reset off voltage 1 Ripple Rejection 1 Load regulation Line regulation Regulator output voltage 2 range Regulator output voltage 2 Regulator reset on voltage 2 Regulator reset off voltage 2 Control Gain Ripple Rejection 2
*note *note
Symbol
Conditions IL=0 200mA IL=200mA,V=7V 9V IL=100mA Pin6=Variation Pin6=Variation Vin=1Vp-p, f=120Hz IL=0 200mA IL=200mA,V=7V 9V IL=100mA IL=100mA,VREGCTL=0V IL=100mA,VREGCTL=1.9V Pin7=Variation Pin7=Variation Vin=1Vp-p, f=120Hz
Min. -80 -20 4.75 2 -80 -20 1.5 1.482 3.135 2 0.75 -
Typ. 0 0 5.0 55 0 0 1.56 3.3 0.95 55
Max. 0 +30 5.25 0.5 SVCC 0 +30 4.5 1.638 3.465 0.5 SVCC 1.15 -
Unit mV mV V V V dB mV mV V V V V V V/V dB
VRL1 VCC1
VREG1 Reson1 Resoff1 RR1
REGULATOR2 CIRCUIT(REGVCC=8V)
VRL2 VCC2
VREG2R VREG2 Reson2 Resoff2 GREGCTL RR2
Note: Guaranteed field.(No EDS/Final test)
13
FAN8036
Application Information
1. Thermal Shutdown
* The TSD circuit is activated at the junction temperature of 160C and deactivated at 135C with the hysteresis of 25C. During the thermal shutdown, the TSD circuit keeps all the output driver off.
SVCC IREF R1 Q0 R2 Hysteresis Ihys R3 Output driver Bias
2. CH Mute Function
* When the mute pin is high, the TR Q1 is on and Q2 is off, so the bias circuit is enabled. When the mute pin is low (GND), the TR Q1 is off and Q2 is on, so the bias circuit is disabled. * During the mute on state, all the circuit blocks except for the variable regulator remain off, and the low power quiescent state is established. * Truth table is as follows; Pin 19, 20 High Low Mute Mute-Off Mute-On
19 20 Q1 MUTE SVCC Bias Blocks (4-CH BTL)
Q2
3. Power Save Function
* When the pin21 is high, the TR Q3 becomes on and Q4 off, so the bias circuit is enabled. When the pin21 is low (GND) , the TR Q3 becomes off and Q4 is on, so the bias circuit is disabled. * During the power save on state, this function keeps all the circuit blocks off, and the low power quiescent state is established. * Truth table is as follows; Pin21 High Low Power Save Power Save Off Power Save On
SVCC M ain Bias
21 Q3
Q4
4. TDS Monitor Function
* Pin 22 is TSD monitor pin, which detects the state of the TSD block and generates the TSD-monitor signal. * In the normal state Q5 is on, and Q6 is off. When the TSD block is activated Q5 becomes off, and thus the voltage of pin22 keeps low. * Truth table is as follows; TSD TSD Off TSD On Pin22 High Low
VCC R(external) SVCC
22 Q6 Q5
20K
14
FAN8036
5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part
40K VREF
43
10K 10K IN+
DO+
37 35 30 28
48 1
3 4
9 10
12
Vin INVp
40K M 40K
13
2
5
11
14
OUT PVCC1(PVCC2) + VDP 60K Vp
10K 10K 40K DO-
36
34
29
27
62K
QP
* The Vref at pin 43 is for eliminating the dc components from the input signals and can set by an exteranl circuit. * The voltage gain from Vin to output is as follows ;
Vin = Vref + V DOP = V D + 4 V DON = V D - 4 V Vout = DOP - DON = 8 V Vout Gain = 20 log ------------ = 20 log 8 = 18dB V
* * * *
Where V means just ac component. The total input to output voltage gain is the sum of the input OP amp network gain and 18dB. The output stage is the balanced transformerless (BTL) driver. The bias voltage Vp is expressed as ;
62k V P = ( PVCC1 - V DP - V CESAT Q P ) x ------------------------- + V CESAT Q P 60k + 62k PVCC1 - V DP - V CESAT Q P = ------------------------------------------------------------------------- + V CESAT Q P 1.97
----------
(1)
15
FAN8036
6. Tray, Changer,panel Motor Drive Part
out 1 24
M
out 2 25
D
D
LEVEL SHIFT 6.0V CTL 15 S.W 0 3.0V VCTL M.S.C V(out1,out2)
IN FWD 16
IN REV 17
* Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as follows; INPUT FWD H H L L REV H L H L OUT 1 Vp H L OUTPUT OUT 2 Vp L H State Brake Forward Reverse Hign impedance
* Where Vp(Power reference voltage) is approximately 3.75V at PVCC2=8V according to equation (1). * Motor speed control (When SVCC=5V, PVCC2=8V) - The maximum torque is obtained when the pin15(CTL) is open. - If the voltage of the pin15 (CTL) is 0V, the motor will not operate. - When the control voltage (pin15) is between 0 and 3.0V, the differential output voltage V(out1,out2) is about two times of control voltage. The output gain is 6dB. - When the control voltage is greater than 3.0V, the output voltage is saturated at the 6.0V because of the output swing limitation.
16
FAN8036
7. Regulator1 Part
REGVCC VREF1 2.5V REGVCC
39
32
REGO1
RES1
6
R1 R2
10K 10K 33uF
* The output voltage of the regulator1 is fixed to 5V. * When power save on or TSD on, regulator1 is disabled. * Truth table is as follows; RES1(Pin6) HIGH LOW REGO1 Active Deactive
17
FAN8036
8. Regulator2 Part
REGVCC VREF2 2.5V REGVCC
39
R EG O 2 4.2V
31
REGO2
1.77V
G ain=0.95
RES2 REGCTL
7
R3 R4
10K 40K 33uF
8
1.56V
0.3V
R E G C TL
* The output of the regulator2 is variable. * The input impedance of the REGCTL pin is 50k. * The REGCTL input circuit is as follows;
VCC FAN8036 R1
8
REGCTL 50K
R2
* The output voltage(VREGO2) is decided as follows;
VREGO 2 = (1.56V + VREGCTL ) x 0.95
* When the REGCTL pin is connect to the ground or open, the regulator output voltage becomse1.56V. * When power save on or TSD on, regulator2 is disabled. * Truth table is as follows; RES2(Pin7) HIGH LOW REGO2 Active Deactive
18
FAN8036
Test Circuits
VCC OP-AMP
IN+ INOUT
REGVCC VREF OP-AMP
IN+ INOUT
PVCC1
48 IN+
47
46
45
44
43
42
41
40
39
38
37 DO1+ DO1DO2+ DO2PGND1 REGO1 REGO2 36 35
IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF 1 2 3 4 5 6 IN1OUT1
OP-AMP
IN-
OPIN2+ OPIN2- OPOUT2 PVCC1 REGVCC
RL1
OUT IN+
RL2
IN2+ IN2OUT2 34 33 32 31
OP-AMP
IN-
OUT
VRES1
IL1
RES1
FAN8036
VRES2 VREGCTL
IN+ 7 8 9 10 11 12 RES2 DO3+ 30 REGCTL IN3+ IN3OUT3 IN4+ IN413 OUT4 14 CTL 15 FWD 16 REV 17 SGND 18 MUTE123 MUTE4 19 20 PS 21 DO329 28 DO4+ DO4PGND2
IL2
RL3
OP-AMP
IN27 26
RL4
OUT
DO5+ 25 TSD-M PVCC2 DO522 23 24
RL5
IN+
IN-
OUT
VCTL OP-AMP
VFWD
VREV
V MU123
VMU4
V PS PVCC2
OP-AMP
IN+ INOUT
SW1
SW2 VCC
SW4 VAC VDC VA VPULSE VB SW3
RL
19
FAN8036
Typical Application Circuits 1
[Voltage control mode]
SVCC
REGVCC PVCC1
48
IN1+
47
OPIN1+
46
OPIN1-
45
OPOUT1
44
SVCC
43
VREF
42
OPIN2+
41
OPIN2-
40
OPOUT2
39
REGVCC
38
PVCC1
37
DO1+
FOCUS
1 2 3 4 5 6
IN1-
DO1- 36
OUT1
DO2+ 35
IN2+
DO2- 34
IN2-
PGND1 33 REGO1 32
TRACKIN G REGO1 REGO2
OUT2
RES1
REGO2
31
FAN8036
VCC
7 8 9 10 11 12
RES2 DO3+
30
M SLED
REGCTL DO3-
29 28
IN3+
DO4+
M
IN3DO4-
27
SPINDLE
OUT3 MUTE123 PGND2
26 25
MUTE4
TSD_M
PVCC2
SGND
OUT4
DO5-
FWD
IN4+ IN4-
DO5+
REV
CTL
PS
13
14
15
16
17
18
19
20
21
22
23
24
M TRAY
PVCC2 VCC
VREF FOCUS TRACKING SLED INPUT INPUT INPUT
SPINDLE INPUT
REG1 RESET
REG2 RESET
TRAY CONTROL
TRAY INPUT
FOCUS TRACKING SLED MUTE
SPINDLE POWER TSD_M SAVE MUTE
[SERVO PRE AMP]
[CONTROLLER]
20
FAN8036
Typical Application Circuits 2
[Differential PWM control mode ]
SVCC
REGVCC
PVCC1
48
IN1+
47
OPIN1+
46
OPIN1-
45
OPOUT1
44
SVCC
43
VREF
42
OPIN2+
41
OPIN2-
40
OPOUT2
39
REGVCC
38
PVCC1
37
DO1+
FOCUS
1 2 3 4 5 6
IN1-
DO1- 36
OUT1
DO2+ 35
IN2+
DO2- 34
TRACKING
IN2PGND1 33 REGO1 32
OUT2
REGO1 REGO2
RES1
REGO2
31
FAN8036
VCC
7 8 9 10 11 12
RES2 DO3+
30
M SLED
REGCTL DO3-
29 28
IN3+
DO4+
M
IN3DO4-
27
SPINDLE
OUT3 MUTE123 PGND2
26 25
MUTE4
TSD_M
PVCC2
SGND
OUT4
DO5-
FWD
IN4+ IN4-
DO5+
REV
CTL
PS
13
14
15
16
17
18
19
20
21
22
23
24
M TRAY
PVCC2 VCC
VREF FOCUS TRACKING SLED INPUT INPUT INPUT
SPINDL E INPUT
REG1 RESET
REG2 TRAY RESET CONTROL
TRAY INPUT
FOCUS SPINDLE POWER TSD_M TRACKING MUTE SAVE SLED MUTE
[SERVO PRE AMP]
[CONTROLLER]
Notes: Radiation pin is connected to the internal GND of the package.
21
FAN8036
Mechanical Dimensions
Package
48-QFPH-1414
17.20 0.30 14.00 0.20
17.20 0.30
14.00 0.20
#48
#1
+0.10 0.30 -0.05 0.10MAX
(0.825)
0.65 3.00MAX 2.60 0.10
+0.10 0.20 -0.05
0.00~0.25
(4.85)
0~8
0.10MAX
0.80 0.20
22
FAN8036
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/22/03 0.0m 001 Stock#DSxxxxxxxx 2003 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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